1. Field of the Invention
The present invention relates to technology of delay analysis in a circuit.
2. Description of the Related Art
In recent years, with the miniaturization of semiconductor integrated circuits, the influence of statistical variations, e.g., process variations, reductions in power supply voltage, and crosstalk, has become considerable, and circuit delay variations have increased. In conventional static timing analysis (STA), circuit delay variations are accommodated by a larger delay margin; however, timing design becomes difficult due to the larger the delay margin.
Therefore, the need for statistical static timing analysis (SSTA) that can reduce such unnecessary delay margins with accurate consideration of statistical variations is increasing. As a delay analysis technique based on SSTA, for example, a technology of performing delay timing analysis with consideration of a correlation of performance between wiring lines or cells in an analysis target circuit has been provided (see, for example, Japanese Patent Application Laid-open No. 2002-279012 and Japanese Patent Application Laid-open No. 2005-092885).
However, according to the conventional technologies, an analysis error that is dependent on an analysis tool (characterizing tool) that estimates delay in each cell, e.g., an error included in an input value or an error that occurs due to an algorithm or a numerical calculation is not considered at all.
Therefore, the delay value that is actually used for a cell in SSTA is a value that includes an analysis error in the original delay variation, and the execution of SSTA utilizing this delay value degrades the overall SSTA analysis accuracy, resulting in a problem that the merit of the fundamental accuracy of SSTA is negated.
FIG. 10 is a schematic illustrating a problem with the conventional technology. As shown in FIG. 10, a probability density distribution P is a delay distribution that is actually used in SSTA of a cell, a probability density distribution Q is a delay distribution accurately representing delay variation of the cell, and a probability density distribution R is a delay distribution concerning analysis error in the cell.
As shown in FIG. 10, the delay distribution that is actually used in SSTA of the cell (probability density distribution P) includes analysis error and is indicative of the accurate delay distribution of the cell (probability density distribution Q) including a delay distribution concerning an analysis error that is dependent on a characterizing tool (probability density distribution R).
Therefore, when the delay distribution of the cell obtained from the characterizing tool is used to execute SSTA, a pessimistic delay distribution is calculated due to the analysis error, and consequently, the circuit design must be adjusted, resulting in a problem of increased burden on the designer and a longer design period.